1. Field of the Invention
The invention relates to a memory device, and more particularly to a memory device comprising stacked memory chips.
2. Description of the Related Art
FIG. 1 is a schematic view showing a 256 Mb memory chip. Referring to FIG. 1, the memory chip 1 comprises 24 address pads A0˜A23, a dummy pad NC, and a selection pad SP. When the memory chip 1 operates as a single memory die, both of the option pad SP and the dummy pad NC are floating. A weak pulling high/low circuit on the inside of the memory chip 1 gradually pulls an internal node which is connected with the option pad SP to a high/low voltage level.
In some applications, two memory chips, such as two memory chips as shown in FIG. 1, can be stacked to form a memory device. One memory chip operates as a top memory chip among the two stacked memory chips, and the other memory chip operates as a bottom memory chip among the two stacked memory chips. At this time, each memory chip requires another address pad serving as the 25th address pad to address the two stacked memory chips. When an access operation is performed by crossing the two stacked memory chips, for example, when an access operation to the top memory chip is finished and then is continuously performed to the bottom memory chip, the top memory chip has to enter into an inactive mode, while the bottom memory chip has to enter into an active mode. On the contrary, when the access operation to the bottom memory chip is finished and then is continuously performed to the top memory chip, the bottom memory chip has to enter into an inactive mode, while the top memory chip has to enter into an active mode. Thus, when a memory chip is designed to be capable of operating as a single memory chip or one of stacked memory chips, controlling switching of the memory chip between an active mode and an inactive mode is an important issue.